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NCV8855
3.00
2.80
Input current
8 V delayed by
No input current
Overlap
2.60
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
0.00%
9.00
10.00
11.00
12.00
13.00
14.00
15.00
16.00
17.00
18.00
20.00% 40.00% 60.00% 80.00% 100.00%
Clock Duty cycle
Figure 23. Irms vs Phase
144deg or 2/5T
5V
Here it is shown that the “sweet spot” phase angle (where
the input RMS current is the lowest) happens at the same
40%
Duty cycle clock
T
Figure 25.
2T
location (in terms of phase relationship) regardless of input
voltage. Thus, once the output voltages are known, a sweet
spot can be determined. After determining the sweet spot,
the input capacitors can be chosen accordingly to handle the
RMS current.
The purpose of interleaving the two SMPS is to eliminate
any overlapping of there input currents. This will reduce the
overall input RMS current. Since the outputs are running at
different voltages, they will have different duty cycles, and
thus running with 180 ° phase difference does not necessarily
guarantee an optimal input RMS current reduction. The
figures below describe, graphically, this point.
Input current
To achieve this optimization, the SYNC function on the
NCV8855 will have to be used with a 40% duty cycle clock.
However, when looking at the worst ? case input RMS
(which occurs at high battery) a 40% duty cycle clock will
yield the same input RMS current as a 50% duty cycle clock.
Thus, the only true benefit of this optimization occurs when
a narrow input voltage range is assured. Therefore, a 50%
duty cycle clock is always recommended.
SMPS Compensation
The NCV8855 utilizes voltage mode control. The control
loop regulates V OUT by sampling V OUT and controlling the
duty cycle. Inherent with all voltage ? mode control loops is
a compensation network.
V IN
Overlap
L OUT
V RAMP
DCR
V OUT
8V delayed by
180deg or 1/2T
5V
PWM
COMPARATOR
C1
R1
ESR
C OUT
R2
C2
C3
R3
COMP
EA
FB
V REF
Figure 26.
50%
Duty cycle clock
T
Figure 24.
2T
The compensation network consists in the internal error
Since the 8 V rail has a wider pulse, with a 50% internal
clock duty cycle, there will be some amount of input current
overlapping which will produce a less than ideal RMS
current. The following figure shows an optimized duty cycle
amplifier and the impedance networks Z IN (R1, R3 and C3)
and Z FB (R2, C1 and C2). The compensation network has to
provide a closed loop transfer function with the highest 0 dB
crossing frequency to have fast response and the highest gain
in dc conditions to minimize the load regulation. A stable
where there is no overlapping.
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